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5
Advanced Information
CY7C1304V25
9-Mb Pipelined SRAM with QDRTM Architecture
Features
* Separate Independent Read and Write Data Ports -- Supports concurrent transactions * 167 MHz Clock for High Bandwidth -- 2.5 ns Clock-to-Valid access time * 4-Word Burst for reducing address bus frequency * Double Data Rate (DDR) interfaces on both Read & Write Ports (data transferred at 333 MHz) @167 MHz * Two input clocks (K and K) for precise DDR timing -- SRAM uses rising edges only * Two output clocks (C and C) accounts for clock skew and flight time mis-matches * Single multiplexed address input bus latches address inputs for both READ and WRITE ports * Separate Port Selects for depth expansion * Synchronous internally self-timed writes * 2.5V core power supply with HSTL Inputs and Outputs * 13x15 mm 1.0 mm pitch fBGA package, 165 ball (11x15 matrix) * Variable drive HSTL output buffers * Expanded HSTL output voltage (1.4V-1.9V) * JTAG Interface
Functional Description
The CY7C1304V25 is a 2.5V Synchronous Pipelined SRAM equipped with QDR architecture. QDR architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations. QDR architecture has separate data inputs and data outputs to completely eliminate the need to "turn-around" the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. Addresses for Read and Write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the CY7C1304V25 Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with 4 18-bit words that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge of both input clocks (K/K and C/C) memory bandwidth is maximized while simplifying system design by eliminating bus "turn-arounds". Depth expansion is accomplished with Port Selects for each port. Port selects allow each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.
Logic Block Diagram
D [17:0] 18
W rite W rite Reg Reg W rite W rite Reg Reg
Read Add. Decode
Write Add. Decode
A(16:0)
A d d re s s Register 17
128Kx18 Array
128Kx18 Array
128Kx18 Array
128Kx18 Array
A dd res s Register
17
A (16:0)
K K
CLK Gen.
Control Logic
RPS C C
Read Data Reg. 72 Control L o g ic 36 Reg. 36 Reg. 18 Reg.
Vref WPS BWS[0:1]
18 Q [17:0]
Selection Guide
7C1304V25-167 Maximum Operating Frequency (MHz) Maximum Operating Current (mA) 167 450 7C1304V25-133 133 350 7C1304V25-100 100 230
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
* 408-943-2600 February 15, 2000
Advanced Information
Pin Configuration
CY7C1304V25 (Top View) 1 A NC 2 Gnd/ 144M Q9 NC D11 NC Q12 D13 VREF NC NC Q15 NC D17 NC TCK 3 NC/ 36M D9 D10 Q10 Q11 D12 Q13 VDDQ D14 Q14 D15 D16 Q16 Q17 A 4 WPS 5 BWS1 NC A VSS VSS VDD VDD VDD VDD VSS VSS VSS A A A 6 K 7 NC 8 RPS 9
CY7C1304V25
10 Gnd/ 72M NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS
11 NC
NC/ 18M NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A
B C D E F G H J K L M N P R
NC NC NC NC NC NC NC NC NC NC NC NC NC TDO
A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C
BWS 0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
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Advanced Information
Pin Definitions
Name D[17:0] WPS I/O InputSynchronous InputSynchronous InputSynchronous Description
CY7C1304V25
Data input signals, sampled on the rising edge of K and K clocks during valid write operations. Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted active, a write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port will cause D[17:0] to be ignored. Byte Write Select 0 and 1, active LOW. Sampled on the rising edge of the K and K clocks during write operations. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written remain unaltered.BWS0 controls D[8:0] while BWS1 controls D[17:9]. BWS0 and BWS1 are sampled on the same edge as D[17:0]. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written into the device. Address Inputs. Sampled on the rising edge of the K clock during active read and write operations. These address inputs are multiplexed for both Read and Write operations. Internally, the device is organized 128K x 72. Therefore, only 17 address inputs are needed to access the entire memory array.These inputs are ignored when the appropriate port is deselected. Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the C and C clocks during Read operations or K and K. when in single clock mode. When the Read port is deselected, Q[17:0] are automatically three-stated. Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K). When active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When deselected, the pending access is allowed to complete and the output drivers are automatically three-stated following the next rising edge of the C clock. The CY7C1304V25 is organized internally as 128K x 72. Each read access consists of a burst of four sequential 18-bit transfers. Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[17:0] when in single clock mode. All accesses are initiated on the rising edge of K. Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q[17:0] when in single clock mode. Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. Q[17:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to VDD, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. TDO for JTAG. TCK pin for JTAG. TDI pin for JTAG. TMS pin for JTAG. Address expansion for 18M. This is not connected to the die. Address expansion for 36M. This is not connected to the die. Address expansion for 72M. This should be tied low on the CY7C1304V25 Address expansion for 144M. This should be tied low on the CY7C1304V25
BWS0, BWS1
A
InputSynchronous
Q[17:0]
OutputsSynchronous
RPS
InputSynchronous
C
Input-Clock
C
Input-Clock
K
Input-Clock
K ZQ
Input-Clock Input
TDO TCK TDI TMS NC/18M NC/36M GND/72M GND/144M
Output Input Input Input Input Input Input Input
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Advanced Information
Pin Definitions (continued)
VREF VDD VSS VDDQ NC InputReference Power Supply Ground Power Supply NC
CY7C1304V25
Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs as well as A/C measurement points. Power supply inputs to the core of the device. Should be connected to 2.5V power supply. Ground for the device. Should be connected to ground of the system. Power supply inputs for the outputs of the device. Should be connected to 1.5V power supply. No connect the device on every rising edge of the output clocks (C and C or K and K when in single clock mode). When the read port is deselected, the CY7C1304V25 will first complete the pending read transactions. Synchronous internal circuitry will automatically three-state the outputs following the next rising edge of the Negative Output Clock (C). This will allow for a seamless transition between devices without the insertion of wait states in a depth expanded memory. Write Operations Write operations are initiated by asserting WPS active at the rising edge of the Positive Input Clock (K). On the following K clock rise the data presented to D [17:0] is latched and stored into the lower 18-bit Write Data register provided BWS[1:0] are both asserted active. On the subsequent rising edge of the Negative Input Clock (K) the information presented to D [17:0] is also stored into the Write Data Register provided BWS[1:0] are both asserted active. This process continues for one more cycle until 4 18-bit words (a total of 72 bits) of data are stored in the SRAM. The 72 bits of data are then written into the memory array at the specified location. Therefore, Write accesses to the device can not be initiated on two consecutive K clock rises. The internal logic of the device will ignore the second Write request. Write accesses can be initiated on every other rising edge of the Positive Input Clock (K). Doing so will pipeline the data flow such that 18-bits of data can be transferred into the device on every rising edge of the input clocks (K and K). When deselected, the write port will ignore all inputs after the pending Write operations have been completed. Byte Write Operations Byte Write operations are supported by the CY7C1304V25. A write operation is initiated as described in the Write Operation section above. The bytes that are written are determined by BWS0 and BWS 1 which are sampled with each set of 18-bit data word. Asserting the appropriate Byte Write Select input during the data portion of a write will allow the data being presented to be latched and written into the device. De-asserting the Byte Write Select input during the data portion of a write will allow the data stored in the device for that byte to remain unaltered. This feature can be used to simplify READ/MODIFY/WRITE operations to a Byte Write operation. Single Clock Mode The CY7C1304V25 can be used with a single clock that controls both the input and output registers. In this mode the device will recognize only a single pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K and C/C clocks. All timing parameters remain the same in this mode. To use this mode of operation, the user
Introduction
Functional Overview The CY7C1304V25 is a synchronous pipelined Burst SRAM equipped with both a Read Port and a Write Port. The Read port is dedicated to Read operations and the Write Port is dedicated to Write operations. Data flows into the SRAM through the Write port and out through the Read Port. The CY7C1304V25 multiplexes the address inputs in order to minimize the number of address pins required. By having separate Read and Write ports, the CY7C1304V25 completely eliminates the need to "turn-around" the data bus and avoids any possible data contention, thereby simplifying system design. Each access consists of 4 18-bit data transfers in two clock cycles. Accesses for both ports are initiated on the Positive Input Clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K) and all output timing is referenced to the output clocks (C and C or K and K when in single clock mode). All synchronous data inputs (D[17:0]) inputs pass through input registers controlled by the input clocks (K and K). All synchronous data outputs (Q[17:0]) outputs pass through output registers controlled by the rising edge of the output clocks (C and C or K and K when in single clock mode). All synchronous control (RPS, WPS, BWS0, BWS 1) inputs pass through input registers controlled by the rising edge of the input clocks (K and K, C and C). Read Operations The CY7C1304V25 is organized internally as a 128Kx72 SRAM. Accesses are completed in a burst of four sequential 18-bit data words. Read operations are initiated by asserting RPS active at the rising edge of the Positive Input Clock (K). The address presented to Address inputs are stored in the Read address register. Following the next K clock rise the corresponding lowest order 18-bit word of data is driven onto the Q[17:0] using C as the output timing reference. On the subsequent rising edge of C the next 18-bit data word is driven onto the Q [17:0]. This process continues until all four 18-bit data words have been driven out onto Q[17:0]. The requested data will be valid 2.5ns from the rising edge of the output clock (C or C, 167MHz device). In order to maintain the internal logic, each read access must be allowed to complete. Each Read access consists of 4 18-bit data words and takes 2 clock cycles to complete. Therefore, Read accesses to the device can not be initiated on two consecutive K clock rises. The internal logic of the device will ignore the second Read request. Read accesses can be initiated on every other K clock rise. Doing so will pipeline the data flow such that data is transferred out of
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Advanced Information
must tie C and C HIGH at power on. This function is a strap option and not alterable during device operation. Concurrent Transactions The Read and Write ports on the CY7C1304V25 operate completely independently of one another. Since each port latches the address inputs on different clock edges, the user can Read or Write to any location, regardless of the transaction on the other port. If the ports access the same location at the same time, the SRAM will deliver the most recent information associated with the specified address location. This includes forwarding data from a Write cycle that was initiated on the previous K clock rise. Read accesses and Write access must be schedule such that one transaction is initiated on any clock cycle. If both ports are selected on the same K clock rise, the arbitration depends on the previous state of the SRAM. If both ports were deselected, the Read port will take priority. If a Read was initiated on the previous cycle, the Write port will assume priority (since Read operations can not be initiated on consecutive cycles). If a Write was initiated on the previous cycle, the Read port will assume priority (since Write operations can not be initiated on consecutive cycles). Therefore, asserting both port selects active from a deselected state will result in alternating
CY7C1304V25
Read/Write operations being initiated, with the first access being a Read. Depth Expansion The CY7C1304V25 has a Port Select input for each port. This allows for easy depth expansion. Both Port Selects are sampled on the rising edge of the Positive Input Clock only (K). Each port select input can deselect the specified port. Deselecting a port will not affect the other port. All pending transactions (Read and Write) will be completed prior to the device being deselected. Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V SS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM, The allowable range of RQ to guarantee impedance matching with a tolerance of +/-10% is between 175 and 350, with VDDQ=1.5V. The output impedance is adjusted every 1024 cycles to adjust for drifts in supply voltage and temperature.
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Advanced Information
Application Example
CY7C1304V25
SRAM #1 D
18
SRAM #4 D
18 18
VTERM=VREF/2
Q C/C K/K Cntr. Add.
Q C/C K/K Cntr. Add.
R=50 W
18 17
Memory Controller
Q Din Add. Cntr. CLK/CLK (input)
72 17 72 2
CLK/CLK (output)
2
R=50 W
VT=VREF/2
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Advanced Information
Truth Table[1, 2, 3, 4, 5]
Operation Write Cycle: Load address, input write data on 2 consecutive K and K rising edges. Read Cycle: Load address, read data on 2 consecutive C and C rising edges. NOP: No Operation Standby: Clock Stopped K L-H RPS H[6] WPS L[7] DQ D(A+00)at K(t+1) DQ D(A+01) at K(t+1)
CY7C1304V25
DQ D(A+10) at K(t+2)
DQ D(A+11) at K(t+2)
L-H
L[7]
X
Q(A+00) at C(t+1)
Q(A+01) at C(t+1)
Q(A+10) at C(t+2)
Q(A+11) at C(t+2)
L-H Stopped
H X
H X
High-Z Previous State
High-Z Previous State
High-Z) Previous State
High-Z Previous State
Note: 1. X="Don't Care", H=Logic HIGH, L=Logic LOW represents rising edge. 2. Device will power-up deselected and the outputs in a three-state condition. 3. "A" represents address location latched by the devices when transaction was initiated. A+00, A+01, A+10 and A+11 represents the addresses sequence in the burst. 4. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode. 5. It is recommended that K = K# and C = C# when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 6. If this signal was LOW to initiate the previous cycle, this signal becomes a "Don't Care" for this operation. 7. This signal was HIGH on previous K clock rise. Initiating consecutive Read or Write operations on consecutive K clock rises is not permitted. The device will ignore the second Read request.
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Advanced Information
Write Cycle Descriptions[1, 8]
BWS0 L L L L H H H H BWS 1 L L H H L L H H K L-H L-H L-H L-H L-H L-H L-H L-H K Comments
CY7C1304V25
During the Data portion of a Write sequence, both bytes (D [17:0]) are written into the device. During the Data portion of a Write sequence, both bytes (D [17:0]) are written into the device. During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered. During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered. During the Data portion of a Write sequence, only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered. During the Data portion of a Write sequence, only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered. No data is written into the device during this portion of a write operation. No data is written into the device during this portion of a write operation.
Note: 8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS0 and BWS1 can be altered on different portions of a write cycle, as long as the set-up and hold requirements are achieved.
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Advanced Information
IEEE 1149.1 Serial Boundary Scan (JTAG - FBGA Only) The CY7C1340 incorporates a serial boundary scan test access port (TAP) in the FBGA package only. The TQFP package does not offer this functionality. This port operates in accordance with IEEE Standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 2.5V I/O logic levels. Disabling the JTAP Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (Vss) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. Test Access Port (TAP) - Test Clock The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register. Test Data Out (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (See Instruction codes). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. Performing a TAP Reset A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a high-Z state. TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the
CY7C1304V25
instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in TAP Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture IR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address, data or control signals into the SRAM and cannot preload the Input or output buffers. The SRAM does not implement the 1149.1 commands EXTEST or
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Advanced Information
INTEST or the PRELOAD portion of SAMPLE / PRELOAD; rather it performs a capture of the Inputs and Output ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in the CY7C1304V25 TAP controller, and therefore this device is not compliant to the 1149.1 standard. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE / PRELOAD instruction has been loaded. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. SAMPLE / PRELOAD SAMPLE / PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the CY7C1304V25 TAP controller is not fully 1149.1 compliant. When the SAMPLE / PRELOAD instructions loaded into the instruction register and the TAP controller in the Capture-DR
CY7C1304V25
state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, he SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold times (TCS and TCH). The SRAM clock inputs might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE / PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the K, K, C and C captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Note that since the PRELOAD part of the command is not implemented, putting the TAP into the Update to the Update-DR state while performing a SAMPLE / PRELOAD instruction will have the same effect as the Pause-DR command. Bypass When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions.
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Advanced Information
TAP Controller State Diagram
CY7C1304V25
1
TEST-LOGIC RESET 0 1 SELECT IR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 EXIT2-IR 1 UPDATE-IR 1 0 0 1 0 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 0 1 0
0
TEST-LOGIC/ IDLE
1
SELECT DR-SCAN 0 1
1
Note: The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
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Advanced Information
TAP Controller Block Diagram
CY7C1304V25
0 Bypass Register Selection Circuitry TDI 2 Instruction Register 31 30 29 . . 2 1 0 1 0 Selection Circuitry TDO
Identification Register 68 . . . . 2 1 0
Boundary Scan Register
TCK
TAP Controller
TMS
TAP Electrical Characteristics Over the Operating Range[9, 10, 11]
Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input and OutputLoad Current GND VI VDDQ Test Conditions IOH = -2.0mA IOH = -100A IOL = 2.0mA IOL = 100A 1.7 -0.3 -5 Min. 1.7 2.1 0.7 0.2 VDD+0.3 0.7 5 Max. Unit V V V V V V A
9. All Voltage referenced to Ground. 10. Overshoot: VIH(AC)12
Advanced Information
TAP AC Switching Characteristics Over the Operating Range[12, 13]
Param tTCYC tTF tTH tTL TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH TCK Clock LOW 40 40 Description
CY7C1304V25
Min. 100
Max
Unit ns
10
MHz ns ns
Set-up Times tTMSS tTDIS tCS TMS set-up to TCK clock rise TDI set-up to TCK clock rise Capture set-up to TCK rise 10 10 10 ns ns ns
Hold Times tTMSH tTDIH tCH TMS Hold after TCK clock rise TDI Hold after clock rise Capture Hold after clock rise 10 10 10 ns ns ns
Output Times tTDOV tTDOX TCK Clock LOW to TDO valid TCK Clock LOW to TDO invalid 0 20 ns ns
Notes: 12. t CS and t CH refer to the set-up and hold time requirements of latching data from the boundary scan register. 13. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
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Advanced Information
TAP Timing and Test Conditions[13]
CY7C1304V25
1.25V 50 W TDO Z0 =50 W CL =20 pF 0V ALL INPUT PULSES 2.5V 1.25V
GND
(a)
tTH
tTL
Test Clock TCK
tTMSS tTMSH
tTCYC
Test Mode Select TMS
tTDIS tTDIH
Test Data-In TDI
Test Data-Out TDO
tTDOX
tTDOV
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Identification Register Definitions
Value Instruction Field Revision Number (31:29) Cypress Device ID (28:12) Cypress JEDEC ID (11:1) ID Register Presence (0) CY7C1304V25 000 01011010011010110 00000110100 1
CY7C1304V25
Description Version number. Defines the type of SRAM. Allows unique identification of SRAM vendor. Indicate the presence of an ID register.
Scan Register Sizes
Register Name Instruction Bypass ID Boundary Scan Bit Size 3 1 32 69
Instruction Codes
Instruction EXTEST Code 000 Description Captures the Input/Output ring contents. Places the boundary scan register between the TDI and TDO. This instruction is not 1149.1 compliant. The EXTEST command implemented by the CY7C1304V25 device will NOT place the output buffers into a HIGH-Z condition. If the output buffers need to be HIGH-Z condition, this can be accomplished by deselecting the Read port. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. The SAMPLE Z command implemented by the CY7C1304V25 device will place the output buffers into a HIGH-Z condition. Do Not Use: This instruction is reserved for future use. Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
IDCODE
001
SAMPLE Z
010
RESERVED SAMPLE/PRELOAD
011 100
RESERVED RESERVED BYPASS
101 110 111
15
Advanced Information
Boundary Scan Order
Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 C C A A A A A A A D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 ZQ Q4 D5 Q5 D6 Q6 D7 Q7 D8 Q8 Reserved GND/72M NC/18M(1) A A NC (0) RPS BWS0 Signal Name 6R 6P 6N 7P 7N 7R 8R 8P 9R 10P 11P 11N 10M 11M 11L 10K 11K 11J 11H 10J 11G 11F 10E 11E 11D 10C 11C 11B 12A (Don't Care) 10A 9A 8B 7C 6C 8A 7B Bump ID 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69
CY7C1304V25
Boundary Scan Order
Bit # K K BWS1 WPS A A NC/36M(1) GND/144M Reserved D9 Q9 D10 Q10 D11 Q11 D12 Q12 D13 Q13 D14 Q14 D15 Q15 D16 Q16 D17 Q17 A A A A A A Signal Name 6B 6A 5A 4A 5C 4B 3A 2A 1A (Don't Care) 3B 2B 3C 3D 2D 3E 3F 2F 2G 3G 3J 3K 3L 2L 3M 3N 2N 3P 3R 4R 4P 5P 5N 5R Bump ID
16
Advanced Information
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................... -65C to +150C Ambient Temperature with Power Applied ................................................-55C to +125C Supply Voltage on VDD Relative to GND........ -0.5V to +3.6V DC Voltage Applied to Outputs in High Z State[14] ............................... -0.5V to VDDQ + 0.5V DC Input Voltage[14] ............................ -0.5V to VDDQ + 0.5V
CY7C1304V25
Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... >200 mA
Operating Range
Range Com'l Ambient Temperature[15] 0C to +70C VDD 2.5+/-100mV VDDQ 1.4V to 1.9V
Electrical Characteristics Over the Operating Range
Parameter VDD VDDQ VOH VOL VIH VIL IX IOZ VREF IDD Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current Input Reference Voltage VDD Operating Supply
[14]
Test Conditions
Min. 2.4 1.4
Max. 2.6 1.9 VDDQ VDDQ/2-0.3 VDDQ+0.3 VREF-0.1 5 5 1.0 450 350 230 100 80 60
Unit V V V V V V A A V mA mA mA mA mA mA
IOH = -2.0mA, Nominal Impedance IOL = 2.0mA, Nominal Impedance
VDDQ/2+0.3 VSS VREF+0.1 -0.3
GND V I VDDQ GND V I VDDQ, Output Disabled Typical Value = 0.75V VDD = Max., IOUT = 0 mA, 6.0 ns cycle, 167 MHz f = fMAX = 1/tCYC 7.5 ns cycle, 133 MHz 10 ns cycle, 100 MHz
-5 -5 0.68
ISB1
Automatic Power-Down Current
Max. V DD, Both Ports De- 6.0 ns cycle, 167 MHz selected, VIN V IH or V IN VIL f = fMAX = 1/tCYC, In- 7.5 ns cycle, 133 MHz puts Static 10 ns cycle, 100 MHz
Note: 14. Minimum voltage equals -2.0V for pulse duration less than 20 ns. 15. TA is the "instant on" case temperature.
17
Advanced Information
Switching Characteristics Over the Operating Range[17]
-167 Param tCYC tKH tKL tKHKH tKHCH tCO tDOH Description K Clock and C Clock Cycle Time Input Clock (K/K and C/C) HIGH Input Clock (K/K and C/C) LOW K/K Clock rise to K/K Clock rise and C/C to C/C rise (rising edge to rising edge) K/K Clock rise to C/C clock rise (rising edge to rising edge) C/C Clock rise (or K/K in single clock mode) to Data Valid[16] Data Output Hold After Output C/C clock Rise (Active to Active) 1.2 Min. 6.0 2.4 2.4 2.7 0.0 3.3 2.0 2.5 1.2 Max
CY7C1304V25
-133 Min. 7.5 3.2 3.2 3.4 0.0 4.1 2.5 3.0 Max
-100 Min. 10.0 3.5 3.5 4.4 0.0 5.4 3.0 3.0 1.2 Max Unit ns ns ns ns ns ns ns
Set-up Times tSA tSC tSD Address set-up to K clock rise Control set-up to clock (K, K, C, C) rise (RPS, WPS, BWS0, BWS1) D[17:0] set-up to clock (K and K) rise 0.7 0.7 0.7 0.8 0.8 0.8 1.0 1.0 1.0 ns ns ns
Hold Times tHA tHC tHD Address Hold after clock (K and K) rise Control Hold after clock (K and K) rise (RPS, WPS, BWS0, BWS1) D[17:0] Hold after clock (K and K) rise Clock (C and C) rise to High-Z (Active to High-Z)[17, 18] Clock (C and C) rise to Low-Z[17, 18] 1.2 0.7 0.7 0.7 0.8 0.8 0.8 1.0 1.0 1.0 ns ns ns
Output Times tCHZ tCLZ Note:
16. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, Vref=0.75V, RQ=250, VDDQ=1.5V, input pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC test loads. 17. t CHZ, t CLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 100 mV from steady-state voltage. 18. At any given voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
2.5 1.2
3.0 1.2
3.0
ns ns
18
Advanced Information
Capacitance[19]
Parameter CIN CCLK CO Description Input Capacitance Clock Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = 2.5V VDDQ = 1.5V Max.
CY7C1304V25
Unit pF pF pF
Note: 19. Tested initially and after any design or process change that may affect these parameters.
VDDQ/2 VREF OUTPUT Device Under Test Z0 =50 W RL =50 W VREF=0.75V VDDQ/2 VREF OUTPUT Device Under ZQ Test 5 pF 0.25V VDDQ/2 R=50 W ALL INPUT PULSES 1.25V 0.75V
[16]
ZQ (a)
RQ=
250 W
1304V25-2
RQ= 250 W (b)
1304V25-3
INCLUDING JIG AND SCOPE
19
Advanced Information
Switching Waveforms
CY7C1304V25
Read/Deselect Sequence
tCYC tKHKH tKHKH tKL tKH tKL
K K
tSA
tKH tHA
A B
A(16:0)
tSC
tHC
Deselect
RPS
tCLZ
Data Out
tCO tKHCH
Q(A)
Q(A+1)
Q(A+2)
Q(A+3)
Q(B)
Q(B+1)
Q(B+2)
Q(B+3)
tCHZ tCO tDOH tDOH
C C
tDOH
Device originally deselected. Activity on the Write Port is unknown. = DON'T CARE = UNDEFINED
20
Advanced Information
Switching Waveforms (continued) Write/Deselect Sequence
CY7C1304V25
tCYC tKL
K
tKH tKL
K
tSD tHD
A B
A
tSC
tH tHC
WPS
tSC tHC
BWSx
Data In
D(A)
D(A+1)
D(A+2)
D(A+3)
D(B)
D(B+1)
D(B+2)
D(B+3)
tSD
tHD
C and C reference to Data Outputs and do not affect Write operations. Activity on the Read Port is unknown. BWSx LOW=Valid, Byte writes allowed, see Byte write table for details. = DON'T CARE = UNDEFINED
21
Advanced Information
Switching Waveforms (continued) Read/Write/Deselect Sequence
CY7C1304V25
K
K
A
A
B
C
D
WPS
RPS
D[17:0]
D(B)
D(B+1)
D(B+2)
D(B+3)
D(D)
D(D+1)
D(D+2)
D(D+3)
Q[17:0]
Q(A)
Q(A+1)
Q(A+2)
Q(A+3)
Q(C)
Q(G+1) Q(C+1)
Q(C+2)
Q(C+3)
C
C
Read Port previously deselected. BWSx assumed active. = DON'T CARE = UNDEFINED
22
Advanced Information
Ordering Information
Speed (MHz) 167 133 100 Ordering Code CY7C1304V25-167BZC/ CY7C1304V25-133BZC/ CY7C1304V25-100BZC/ Package Name BA165A Package Type 13 x 15 mm FBGA
CY7C1304V25
Operating Range Commercial
Document #: 38-00925-**
Package Diagram
(c) Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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